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This brief presents a highly linear and high-speed operational amplifier that consists of a double-recycling folded cascode input stage and an adaptive biasing with a flipped voltage follower to boost… Click to show full abstract
This brief presents a highly linear and high-speed operational amplifier that consists of a double-recycling folded cascode input stage and an adaptive biasing with a flipped voltage follower to boost slew-rate and unity-gain frequency. In addition, frequency compensation is performed by an input cross-coupled phase-lead passive compensation scheme and hybrid Miller-cascode compensation. A 56 MHz −3 dB bandwidth fifth-order programmable gain continuous-time active low pass filter is fabricated in 180 nm CMOS to validate the proposed scheme. The filter achieves 30.5 dBm of third-order interception point at 38 MHz and occupies 0.215 mm2. The filter consumes 14.7 mW with 1.8 V supply and has 0.2 dB in-band ripple.
Journal Title: IEEE Transactions on Circuits and Systems II: Express Briefs
Year Published: 2021
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