LAUSR

This brief proposes a novel current output resistor string DAC architecture implemented for a 10-bit resolution. The DAC consists of a 6-bit coarse resistor string DAC followed by a 4-bit multi-input interpolation amplifier, and a voltage to current conversion stage. Use of a multi-input interpolation amplifier with shared resistive load provides accurate fine conversion with reduced resistor count. The current output DAC has high output impedance from the regulated current source architecture. The prototype was fabricated in a 0.18 $\mu \text{m}$ CMOS process technology. The measured integral non-linearity (INL) and differential non-linearity are 0.5 LSB and 0.4 LSB, respectively. The chip consumes static power 0.54 $mW$ at 1.8 $V$ supply and occupies 0.042 $mm^{2}$ area.