LAUSR

This brief presents a design of fast frequency locking 320 Mb/s to 2.7 Gb/s continuous-rate reference-less clock and data recovery (CDR) circuit. A simultaneous coarse/fine frequency acquisition processes are being done to achieve an unrestricted frequency acquisition range and a fast frequency acquisition time. The CDR is implemented in a 180 nm CMOS process, consumes 62 mW of power including I/O buffers at 2.7 Gb/s with a 1.8 V supply. The CDR takes 15.2 $\mu \text{s}$ of a maximum locking time when the data rate locked at 2.7 Gb/s is switched to 320 Mb/s. The CDR circuit has shown 59 ps and 75.4 ps peak-to-peak jitter in recovered clock and data, respectively, with 2.7 Gb/s input data.