This brief introduces a self-biased Scalable Low-Voltage Signaling (SLVS) receiver circuit in order to minimize the power dissipation on D-PHY layer of the Mobile Industry Processor Interface (MIPI). This design… Click to show full abstract
This brief introduces a self-biased Scalable Low-Voltage Signaling (SLVS) receiver circuit in order to minimize the power dissipation on D-PHY layer of the Mobile Industry Processor Interface (MIPI). This design does not require any static bias circuitry. It can also support an input common-mode voltage of the receiver as low as 50 mV. This allows D-PHY transmitter to use lower common-mode voltage further reducing the power dissipation of the transceiver pair of D-PHY layer. It is fabricated in a 180-nm CMOS process. The test results show that it operates up to 2 Gbps at 1.2 V power supply in High Speed-mode (HS-mode) of MIPI D-PHY standard. The power efficiency is 92
               
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