LAUSR

In this brief, a four-phase delay-locked loop (DLL) with low phase error, low power consumption, and small area is presented for time-to-digital conversion application. A highly matched single-ended differential single-ended voltage-controlled delay line is proposed to improve the phase uniformity of these multiple output signals. A digital auxiliary duty-cycle corrector is designed to adjust the width of the output signal to reduce the pulse width error and to make the duty cycle of each output signal approximately 50%. Designed using 0.18- $\mu \text{m}$ CMOS technology, this DLL occupies an active area of 111.32 $\mu \text{m}\,\,\times $ 82.74 $\mu \text{m}$ . With a 1.8 V supply voltage and a 250 MHz operating frequency, the measured power consumption and output phase error rate of this DLL are 2.28 mW and 1.3%, respectively.