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A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional Stages

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This work presents a low-noise millimeter-wave fractional-N digital frequency synthesizer architecture. It is formed by cascading an injection-locked frequency multiplier, an open-loop digital frequency synthesizer and an integer-N LC digital… Click to show full abstract

This work presents a low-noise millimeter-wave fractional-N digital frequency synthesizer architecture. It is formed by cascading an injection-locked frequency multiplier, an open-loop digital frequency synthesizer and an integer-N LC digital phase-locked loop. Though the individual blocks are not novel, the combination synergically achieves a stable low-noise performance by leveraging the merits of three functional stages while suppressing the demerits of them without any complicated calibration or time-consuming optimization. The implemented frequency synthesizer in 40nm CMOS process shows an integrated jitter of 196fs with an in-band phase noise of −93.5dBc/Hz at a 100kHz offset and an in-band fractional spur of −59.4dBc.

Keywords: digital frequency; frequency; noise; fractional digital; frequency synthesizer

Journal Title: IEEE Transactions on Circuits and Systems II: Express Briefs
Year Published: 2021

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