LAUSR

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a $0.18~\mu \text{m}$ CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is proposed. The auxiliary-capacitor based calibration technique eliminates the need for a dedicated reference buffer to generate the calibration voltages at all the comparator thresholds. By switching the auxiliary capacitor and doing some simple calculation work, all the capacitor mismatches in the first and second stages are corrected in the digital domain, thereby significantly improving the ADC performance. Measurement results show that, with 70.1 MHz input, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 75.5 dB to 77.8 dB, and the spurious-free-dynamic-range (SFDR) is improved from 81.9 dBc to 90.5 dBc with the proposed calibration technique.