LAUSR

Recent work has shown that small, fast, and power-efficient multiple constant multiplication (MCM) implementations can be realized on FPGAs rather than requiring specialized embedded multipliers. However, the limited silicon area on FPGAs requires applications such as image processing to frequently exchange the multiplier (filter) blocks in a series of filtering operations, and no previous works have considered the MCM problem under topological constraint to avoid time-consuming partial reconfiguration on FPGAs. In this brief, we define a unified MCM (UMCM) problem of finding a unified hardware topology for the multiplier blocks frequently exchanged and introduce a framework termed compatible graph synthesis to solve the problem efficiently. Using a set of parameters to logarithmic shifters, dynamic exchange of multiplier blocks with the unified topology can be realized without partial reconfiguration on FPGAs. Experimental results show that the solution is valuable for applications that require frequent exchange of multiplier blocks on FPGAs due to a limited silicon area budget.