LAUSR

A CMOS analog multiplier with a large signal bandwidth has been proposed. The multiplier is based on a variable-gain amplifier and the gain is controlled continuously in accordance with an input signal. A continuous-time inverter-based flash digitizer with no need of an oversampling clock serves as an enabler for the enhanced bandwidth with robust operation. The two-quadrant and four-quadrant multipliers are presented as well as a divider with the same principle. The proposed four-quadrant multiplier was designed with $0.13~\mu \text{m}$ CMOS process under a 1.2V supply. Simulation results proved multiplication of 100MHz input signals with 7.0mW power at typical condition. In addition, calibration of the digitizer was applied and verified under process variation. Furthermore, the divider and a fusion of the multiplier and the divider were also designed and confirmed by simulations. Since the multiplier and the divider are suitable for low-voltage operation and require no well-defined square or exponential property of MOS transistors, a larger bandwidth or lower power is expected by implementation with finer CMOS process.