LAUSR

The CMOS scaling and power usage limitations make the calibration techniques inevitable in the design and implementation of pipeline analog-to-digital converters (ADCs) especially in high speed and high-resolution applications. In this brief, a new digital method is introduced which requires only a shift register and some logic blocks compared to traditional correlation-based background techniques meanwhile improving converter’s characteristics superior to prior methods. Here, two techniques are introduced to calibrate the linear and third-order non-linearities of the gain stages. Making use of the proposed algorithm, to the best of our knowledge, both the linear and non-linear errors in the multiplier digital-to-analog converter (MDAC) are estimated with lower number of conversion samples compared to the correlation-based reported methods. To verify and test the effectiveness of this new method, a model of 12-bit, 100 MS/s pipeline converter is calibrated through simulation. As a result, 21 dB and 25 dB improvements are achieved in behavioral simulated results of SNDR and SFDR respectively through about $1\cdot 8 \times 1 0^{6}$ conversion cycles and, INL and DNL of the ADC, are tuned to about +0.2/−0.3 LSB and +0.18/−0.11 LSB, respectively.