LAUSR

A fast-locking phase-locked loop (PLL) using the proposed phase error compensator (PEC) is presented. The PEC compensates the accumulated phase error during the frequency acquisition process to enhance the settling time of this PLL. This PLL is fabricated in a 40-nm CMOS process. The output frequency of the PLL ranges from 2 to 3 GHz. When this PLL is switched from 2 GHz to 3 GHz, the measured settling time using the PEC is 0.6us which is around 30 reference clock cycles. The power consumption of the PLL is 4.6mW at 3 GHz for a supply of 1V. The integral root-mean-square jitter over 1 kHz to 100 MHz is 2.99ps.