LAUSR

A reference-less sub-baud-rate linear clock and data recovery with a frequency acquisition is proposed to operate from 6 to 11 Gb/s. The proposed frequency acquisition technique operating at a single differential quarter-rate clock and sharing the same phase detector achieves low power consumption. Fabricated in a 28-nm CMOS technology, the frequency detection (FD) logic and locked detector (LD) consume only 0.62 mW. Furthermore, the proposed sub-baud-rate linear phase detector with dead zone free guarantees the in-band recovered phase noise and needs no accuracy reference voltage threshold for phase locking. The proposed sub-baud-rate CDR consumes 8.66 mW, corresponding to power efficiency of 0.86 pJ/bit at 10 Gb/s.