LAUSR

In this brief, we combine a buffered asymmetric dual-path structure with cascode Miller compensation to extend the unity-gain bandwidth of a three-stage amplifier while decreasing its power consumption. This design is implemented in a 65 nm CMOS technology with 0.0017 mm2 chip area and 6.62 ${\mu }\text{W}$ power consumption. Post-simulation results achieve ${>}100$ dB DC gain, 1.20 MHz UGB, and 0.391 V/ ${\mu }\text{s}$ SR with a 1.5 nF load capacitor.