LAUSR

This brief presents a compact and flexible 0.73–15.5GHz clock generator with only a single LC-VCO. A 50% duty cycle divide-by-1.5 divider (Div-1.5) is employed to reduce the required VCO tuning range in the wide-range clock generator to 50%, which becomes viable for a single LC-VCO to cover. The divider is realized by duty cycle interpolation (DI) between two digital divide-by-1.5 (DDiv-1.5) clocks with 33.3% duty cycle and 66.7% duty cycle, respectively. The clock generator was fabricated in 12nm CMOS process with an active area of 0.17 mm2. At a 13.28125GHz output, it achieves a 101fs integrated jitter and a −74.79dBc reference spur, while consuming 19.5mW. The measured worst deterministic jitter induced by the 50% duty cycle Div-1.5 is 550fs.