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The maximum tolerable clock jitter for high-speed ADCs is pessimistically predicted by Nyquist-rate input sinusoidal tests. We prove that the jitter can be greatly relaxed in the presence of lossy… Click to show full abstract
The maximum tolerable clock jitter for high-speed ADCs is pessimistically predicted by Nyquist-rate input sinusoidal tests. We prove that the jitter can be greatly relaxed in the presence of lossy channels in wireline systems. We derive compact expressions that allow PLL designers to decide how much jitter can be tolerated for a given channel loss and symbol rate.
Keywords:
bounds adc;
performance bounds;
jitter;
adc based;
clock jitter
Journal Title: IEEE Transactions on Circuits and Systems II: Express Briefs
Year Published: 2023
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Journal Title: IEEE Transactions on Circuits and Systems II: Express Briefs
Year Published: 2023
Link to full text (if available)
Share on Social Media: Sign Up to like & get
recommendations!