Many multipliers based on approximate compressors have been developed for error-tolerant applications such as image processing to reduce power, but the combination of them has not been fully studied. This… Click to show full abstract
Many multipliers based on approximate compressors have been developed for error-tolerant applications such as image processing to reduce power, but the combination of them has not been fully studied. This brief proposes a novel 4 gate 4–2 approximate compressor which is complementary with other compressors from earlier work and constructs a hybrid multiplier based on the compressors, a constant approximation, and error correction AND gate. According to the simulation results, the proposed hybrid approximate multiplier has excellent accuracy and electrical performance tradeoff and reduces the power-delay-area product (PDAP) by 66% with an MRED of 2.5% when compared to the exact multiplier.
               
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