LAUSR

This brief presents two improved concepts for self-biased current references. The first approach consists of a current loop with not only one linear and one nonlinear current mirror, but with two stacked complementary nonlinear current mirrors. By this, noise, mismatch and impact of supply voltage variation can be reduced by up to a factor of 2 (6 dB). The second approach is designed and manufactured for test purposes in a 0.18 $\mu $ m 3.3V standard CMOS technology and consists of multiple nonlinear current mirrors connected in series within a loop. An evaluation of 20 die-to-die prototypes of this novel current reference concept shows that current noise, local transistor mismatch and impact of supply voltage variation can be reduced by up to 6 dB with two nonlinear current mirrors connected in series and by up to another 3 dB with each additional nonlinear current mirror. Furthermore, the suppression of global process tolerances can be significantly improved in both approaches by using nonlinear current mirrors, each consisting of a different type of transistor with uncorrelated oxide thickness statistics between these different transistor types. A Monte Carlo lot-to-lot simulation in the 0.18 $\mu $ m CMOS technology with a sample size of 1000 shows that the expected worst-case tolerance ( $\pm 3\sigma $ /mean) of those current references should be smaller than ±7%.