LAUSR

Pedestrian detection is an important issue in an intelligent transportation system and involves complex hardware architecture. This high complexity and low detection accuracy make it a prompt topic of research. This paper proposes a novel feature extractor with its efficient hardware implementation for the real-time pedestrian detection system. The proposed approach termed here as Histogram of All Significant Gradients (HASG) improves the Histogram of Significant Gradients (HSG) technique by the inclusion of diagonal gradients. The diagonal gradients give an add-on feature which improves the detection accuracy of the detection system. The overhead of extra computation is compensated here by the proposition of a hardware architecture that utilizes only integer computation. The arctangent operation which is a floating-point operation is replaced here by a simplified architecture that uses only integer computation units. The proposed hardware architecture is found to have 73.65% reduced hardware consumption in contrast to the existing one. The complete design is implemented on the Artix-7 FPGA device with a maximum achievable clock frequency of 115 MHz.