LAUSR

The growing concern of single event upset (SEU) in sub-20 nm CMOS technology based field-effect transistors (FETs) has become a key challenge. Therefore, in this paper we have investigated performance degradation of digital benchmark circuits due to SEU for the conventional junctionless transistor (JLT) and dopingless JLT (DL-JLT). For device-circuit interaction, we have developed the lookup table based Verilog-A models of both devices. The circuit simulation results show that the critical linear energy transfer (LET) of DL-JLT based 6T SRAM cell is $\sim 3.2\times $ higher when compared to conventional JLT based 6T SRAM cell at $V_{DD} = 0.9$ V. The single event upset electrical masking efficiency of a five-stage inverter chain of FO1 (fan-out-one) based on DL-JLT exhibits significantly higher ( $\sim 33\times $ ) than its counterpart based design. Therefore, the results presented in this paper provide an opportunity for future digital logic bench mark circuits designing using DL-JLT for heavy ion irradiation environment.