LAUSR

The combined impact of process- and substrate-induced stress has been analytically modeled for a rectangular fin inserted into an insulator-on-silicon (IOS) substrate. Stress estimation and profiling are performed for different fractional insertion of the fin into the IOS substrate and the induced stress values are observed to saturate for ≥1/3 of the fin insertion. Therefore, a one-third of inserted Si fin is used to estimate the induced stress by following a standard FinFET process flow. Uniaxial compressive stress as high as 4.6 GPa has been obtained, and it has also been observed that the hole mobility can be enhanced to a significantly high value by judiciously choosing the gate dielectrics and fractional insertion of the fin. Thereby, the design of symmetric CMOS by using such mobility-enhanced p-FinFET is possible. Moreover, the current–voltage characteristics of such strain-engineered p-FinFETs exhibit improved drain-induced barrier lowering and subthreshold swing and ~45% enhancement of drain current.