LAUSR

Proper driving of a large-area, high-resolution, and high-frame-rate active-matrix display can be hindered by excessive delay along a signal path, such as a scan line. Depending on the transistor architecture, such delay could be dominated by the parasitic overlap capacitance between the gate electrodes and the source/drain (S/D) regions of the address-transistors attached to a scan line. While the capacitance can be minimized by employing a transistor with the edges of the regions self-aligned (SA) to those of the electrode, actual implementation is easier with a top-gate rather than the more commonly deployed bottom-gate architecture. Presently reported is the realization and characterization of a bottom-gate, SA indium–gallium–zinc oxide transistor. The extent of the overlap between the S/D and the gate is determined by a thermal “activation” process, similar to how it is controlled in a conventional top-gate, SA transistor.