LAUSR

A physics-based threshold voltage model of junction-less (JL) double gate (DG) FETs with vertical structural and doping asymmetry is being proposed in this paper. The numerical implementation of vertical asymmetric doping in the FET devices modeling has been studied extensively. A linear approximation, as suggested in the post-annealed implantation technique, is introduced to account for asymmetric-doped profile falling within the channel thickness. Furthermore, Bhaskar’s approximation of sinusoidal has been implemented in the solution to impart due accuracy in the modeling overextended range of device parameters. Overall, appropriate implementation of these mathematical techniques has reduced the complexity of the full evanescent mode analysis immensely and has together retained the accuracy in the solution. The simplicity of the model has provided flexibility to study structural and doping asymmetry together for JL DG FET. Synopsys Sentaurus Device simulation tool has been used for verification of the model results.