LAUSR.org creates dashboard-style pages of related content for over 1.5 million academic articles. Sign Up to like articles & get recommendations!

Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

Photo from wikipedia

In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed based on a charge-based model. Interface charge traps arising from… Click to show full abstract

In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed based on a charge-based model. Interface charge traps arising from exposure to chemicals, high-energy ionizing radiation, or aging mechanism could degrade the charge–voltage characteristics. The model is predictive in a range of temperatures from 77 to 400 K. The validity of the approach is confirmed by extensive comparisons with numerical technology computer-aided design (TCAD) simulations in all regions of operation from deep depletion to accumulation and from linear to saturation.

Keywords: traps junctionless; charge traps; interface charge; charge; modeling interface

Journal Title: IEEE Transactions on Electron Devices
Year Published: 2019

Link to full text (if available)


Share on Social Media:                               Sign Up to like & get
recommendations!

Related content

More Information              News              Social Media              Video              Recommended



                Click one of the above tabs to view related content.