LAUSR

Interconnection technologies must consider reliability problems in dense on-chip networks, where a large number of routing elements constitute the global tracks for bus transactions through high-speed and low-swing signals. As the density of device integration continues to evolve and even employ multilevel states, technologies must effectively cope with dynamic errors to maintain system reliability. The primary objective of this study is to develop an atomic hardware multiplexer to decrease signal errors that can be applied to fault-tolerant routing resources in the digital domain. We propose a new bus coding method named bit-basis code division multiplexing (BCDM) and multidimensional expansions to integrate multi-source digital signals. The concurrent multiplexing techniques offered here can enhance the random noise immunity of the existing differential and duplicating bus transactions. Additionally, we demonstrate that simple parity and receiving integration improve the applicability of the BCDM. In numerical simulations, the proposed BCDM variants exhibited lower error rates and fewer transmission costs than existing methods. In a mesh-type spiking neural network, these methods can be used to multiplex the individual router taps and provide immunity from random noise. In a 32-nm CMOS technology library, the gate-count overhead of the multiplexing operators was only 3.6 percent of the baseline design.