LAUSR

With the emergence of new power semiconductor devices, the switching speeds in power converters are increasing. The stray inductances of switching cells must, therefore, be minimized to limit overvoltages on transistors. One relatively new approach, called power chip-on-chip (PCoC), considers the integration of power dies, one on top of the other, directly in the busbar. This allows for the reduction of the stray inductance. This paper first presents the implementation of a PCoC module using classical packaging techniques. Then, a description of the different technological steps for the realization is outlined. Finally, experimental characterization results confirm the lower stray inductances offered by the PCoC package compared with the planar one.