LAUSR

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this work, we demonstrate a GaN-based gate driver with an over-current (OC) protection circuit and under-voltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, over-current protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power device. The over-current protection is implemented with a separated sensing branch and blanking time controller and the response time to an over-current event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V and its threshold voltage is specially tailored for the GaN integrated circuits.