LAUSR

This work presents a reconfigurable RF frequency synthesizer implemented with the field-programmable gate array (FPGA) and the digital-controlled oscillator (DCO) fabricated in a 0.18- $\mu \text{m}$ CMOS technology. The frequency synthesizer uses a fractional frequency ratio calculator (FRC) to measure the DCO output frequency and realize frequency locking. Due to the FRC, the correlation of the DCO frequencies and its control codes can be characterized and stored in a lookup table (LUT) of the FPGA without the need of external measurement instruments. When requested to settle at a new frequency, the synthesizer looks for the DCO control code from the LUT and performs the frequency-locking routine. The synthesizer covers a wide frequency output range from 496 to 2470 MHz with the resolution of 195 kHz and achieves a settling time of 32.5–45 ns.