LAUSR

For the past ten years a new emerging branch of computer science is making unprecedented efforts to create arithmetic circuits based on a new class of parallel computing in order to improve the area consumption and speed processing of the existing binary circuits. Inspired by the neural processing of the soma and transmission of the information between neurons, a new class of neural computing models (spiking neural P systems) has been proposed. Most of the current neural arithmetic circuits perform addition, subtraction, multiplication, division and logic gates expending several neurons and synapses per each circuit with complex rules. In this work, we propose four single neuron arithmetic circuits to create compact circuits which potentially can be used in portable applications such as mobile robots, mobile devices, among others. Taking ideas from various neurobiological phenomena such as dendritic delays, dendritic feedback, astrocyte-like control and dendritic growth, we have designed these circuits with simple and homogenous rules and the connectivity of each neuron requires few numbers of synapses. Hence, the proposed neural circuits increase the processing speed and decrease the area consumption compared with previously reported solutions based on SN P systems. In addition, the proposed neural circuits have been integrated in a single, configurable, multi-circuit processor. This processor was implemented in a Stratix V GX FPGA to demonstrate their efficiency in terms of processing speed and area consumption.