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This paper proposes a hybrid data ordering algorithm which executes serial and parallel instructions. The implementation of the system is presented in the Zedboard development board of Xilinx that includes… Click to show full abstract
This paper proposes a hybrid data ordering algorithm which executes serial and parallel instructions. The implementation of the system is presented in the Zedboard development board of Xilinx that includes a SoC (System on Chip). The design was done in high level language HLS (High Level Synthesis). It receives a vector of N elements and delivers the set of indexes of the L major elements ordered. The complexity of the algorithm is analyzed in a generic way. The required times and resources are evaluated and compared with well known sorting algorithms.
Journal Title: IEEE Latin America Transactions
Year Published: 2019
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