LAUSR

This paper presents a balanced frequency doubler with 6.5-dBm peak output power at 204 GHz in 130-nm SiGe BiCMOS technology ( $f_{T}/f_{\max }=210$ /250 GHz). To convert the single-ended input signal to a differential signal for balanced operation, an on-chip transformer-based balun is employed. Detailed design procedure and compensation techniques to lower the imbalance at the output ports, based on mixed mode S parameters are proposed and verified analytically and through electromagnetic simulations. The use of optimized harmonic reflectors at the input port results in a 2-dBm increase in output power without sacrificing the bandwidth of interest. The measured conversion loss of the frequency doubler is 9 dB with 6-dBm input power at 204-GHz output. The measured peak output power is 6.5 dBm with an on-chip power amplifier stage. The 3-dB output power bandwidth is measured to be wider than 50 GHz (170–220 GHz). The total chip area of the doubler is 0.09 mm2 and the dc power consumption is 90 mW from a 1.8-V supply, which corresponds to a 5% collector efficiency.