LAUSR

A frequency multiplier for the direct generation of the fourth, sixth, or eighth harmonic of an input signal in a single stage is presented. By analyzing the effect of clipping both half-waves in the output signal asymmetrically, beneficial clipping thresholds are identified. Based on the ideal signal analysis, circuit simulations are carried out to investigate and implement the proposed approach using a heterojunction bipolar transistor (HBT) push–push cascode amplifier, which enables the independent adjustment of the clipping thresholds. Finally, the circuit is combined with an input balun and an output amplifier and fabricated in a 130-nm SiGe BiCMOS process for verification. Measurement results of the prototype are compared with simulations based on available VBIC and HICUM models for the HBTs, providing insight on their capabilities to predict the high-order nonlinear effects essential for the operation of the presented multiplier. The circuit performs in general agreement with the HICUM model simulations and represents a versatile times-four, times-six, and times-eight frequency multiplier with a 37-GHz output-referred bandwidth from 173 to 210 GHz and an output power of up to −6 dBm. To the the best of the authors’ knowledge, the conversion gain of 10 dB is the highest in class reported up to date, even when compared to III/V-based circuits. A maximum harmonic suppression of 40 dB and a total dc power consumption of 63 mW are measured.