A high-precision delay chain circuit integrated in a 0.18- $\mu \text{m}$ CMOS technology working in the frequency bandwidth of 8–18 GHz has been designed and tested. The designed delay control… Click to show full abstract
A high-precision delay chain circuit integrated in a 0.18-$\mu \text{m}$ CMOS technology working in the frequency bandwidth of 8–18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay cell has larger delay-bandwidth product and is less prone to parasitic capacitances of inductor elements compared with conventional passive second-order APN delay cells. The fabricated chip utilizing the novel delay cell occupies an area of $0.9\times3.6$ mm2 and consumes 115.5- and 13.5-mW dc power from a 3.3-V voltage supply in its high- and low-power modes, respectively.
