This article describes a single-pole, single-throw (SPST) CMOS switch aimed at integrated transceiver applications. The SPST switch realizes better than 50-dB isolation (ISO) across dc-to-43 GHz while maintaining an insertion… Click to show full abstract
This article describes a single-pole, single-throw (SPST) CMOS switch aimed at integrated transceiver applications. The SPST switch realizes better than 50-dB isolation (ISO) across dc-to-43 GHz while maintaining an insertion loss (IL) below 3 dB. To maximize ISO, substrate coupling is compensated using bilateral RF signal cancellation in a fully differential circuit topology. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype is fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology and has an active area of 0.0058 mm2. Monte Carlo simulations predict variations due to processing of 8.3% and 2.75% in IL and ISO, respectively, ±0.2 dB variation (for both IL and ISO) from a 5% change in supply voltage, and ±0.1-dB variation (both IL and ISO) for a 0 °C–85 °C temperature sweep.
               
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