LAUSR

STT-MRAM has received wide attention with its promising properties as the next generation memory. Over the years, with entering into nanometer technology, as process-temperature-voltage (PTV) variations being intensified increasingly, the read reliability of STT-MRAM becomes a critical problem. Therefore, it is highly required to design a sensing circuit with good sensing margin (SM) and anti-interference. This paper presents a dynamic reference (DR) and variation-tolerant sensing circuit for deep nanometer STT-MRAM. The circuit is composed with a clamp voltage generator (CVG), a dynamic reference generator (DRG), and a fully differential charge transfer amplifier (FDCTA). It is demonstrated that the proposed sensing circuit is capable of immunizing the PTV variations by increasing the sensing margin (SM) while lowering the read disturbance (RD). The sensing margin of the proposed circuit can be as high as 312 mV on condition of VDD to be 1.2 V and TMR value to be 150%.