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Low-Power Front-End ASIC for Silicon Photomultiplier

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Thanks to its compact structure, mechanical endurance, and low bias voltage, the silicon photomultiplier (SiPM) can be used in small-size applications which require reduced power consumption. In order to detect… Click to show full abstract

Thanks to its compact structure, mechanical endurance, and low bias voltage, the silicon photomultiplier (SiPM) can be used in small-size applications which require reduced power consumption. In order to detect the light intensity as low as a single photon, the front-end electronics has to amplify and shape the signal of the photodetector. The low-power design cannot impair the performance of readout electronics or limit the capabilities of the SiPM itself. This paper presents a two-channel integrated circuit (IC) designed in Austria Mikro Systeme CMOS 350-nm technology dedicated for the SiPM-based applications. The input stage is a super-common-gate architecture. Each channel of the IC consists of an amplifier and a peak detector with an offset reduction circuit. The power consumption of the single channel is less than 3 mW from the single voltage supply (3.3 V). Moreover, the number of channels of the IC can be easily increased thanks to small dimensions of the circuit. This paper presents a detailed analysis of the IC including: noise performance with adjustment of the input transistor’s size, transient and dc simulations of the amplifier and the peak detector, and the introduction of a simple offset reduction technique for the peak detector. The measurement results obtained with two SiPM detectors are presented.

Keywords: front end; low power; silicon photomultiplier; power

Journal Title: IEEE Transactions on Nuclear Science
Year Published: 2018

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