LAUSR

Radiation-induced single-event transients (SETs) are the leading cause of mal-operations in CMOS nanometric integrated circuits. The increasing complexity of advanced CMOS digital circuits makes SET effects investigation a rising challenge. In this work, we propose a 3-D-oriented simulation approach able to model the passage of heavy ion particles through the physical structures of modern digital circuits implemented with ultrananometric manufacturing processes. The proposed approach is able to generate the transient voltage pulse in response to a heavy-ion track and identify the effects of the sensitive volume and contact structure. We present heavy-ion radiation test experiments performed on a 65-nm Flash-based CMOS technology process and, as proof-of-concept, we successfully compared the SET cross sections showing comparable results.