LAUSR

In a three-stage cascaded modular solid state transformer (CMSST), unbalanced dc bus voltages at the output of cascaded multilevel rectifier is a common issue due to inevitable parameter mismatch in stage-2. To balance the dc bus voltages, either voltage balance control (VBC) in stage-1 or power balance control (PBC) in stage-2 is necessary. In this paper, an in-depth theoretical analysis to investigate the input power quality of the CMSST in the presence of voltage and PBC schemes is presented. The grid-side multilevel voltage of the CMSST is analyzed to highlight the limitation of using VBC in stage-1. It is then mathematically proven that the switching frequency based harmonics in the grid current are significantly reduced by using the PBC in stage-2. Simulation studies of a 3.3-kV, 50-kVA CMSST are carried out using the PLECS software to substantiate the proposed analysis. Experimental verifications are performed on a 750-VA single-phase CMSST laboratory prototype for a 20% parameter mismatch in stage-2. It is found that the grid current total harmonic distortion (THD) is reduced from 6.65% to 3.8% at 50% load by using PBC in stage-2. This paper provides guidelines for the designer to choose appropriate balance controllers for the CMSST.