LAUSR

One way to achieve the best in class reliability is the implementation of a design for reliability methodology into the design process in order to estimate the lifetime of each individual critical component, based on proper reliability models for failure modes. The main drawback of the above-mentioned approach is that it relies on handbook-based reliability models, which usually are only accurate for particular components. This fact causes the necessity to develop a testing procedure for SiC power metal-oxide semiconductor field-effect transistor (MOSFET), to determine its reliability model parameters. Such model could be further implemented in the design for reliability methodology for the high-performance power supply design process. In this article, a cost effective and industrial friendly laboratory setup for active power cycling of SiC power MOSFETs in SOT-227b housing is presented. By this example, various control strategies for accelerated lifetime testing, degradation indicators for wear-out condition monitoring and junction temperature estimation methods are compared on their impact on test results and complexity in either laboratory setup and its maintenance procedure. Technical issues related to the start-up of active power cycling test and failure detection algorithm are discussed. Finally, test results for SiC power MOSFETs subjected to over 63355 power cycles are presented.