LAUSR

The utilization of wide band-gap semiconductor devices provides the possibility of higher switching frequency and power density for power converters. However, the influence of parasitic parameters becomes more significant. It deteriorates the converter performance and leads to extra loss. In this article, the extra loss caused by the parasitic capacitance of printed circuit boards (PCBs) is studied. The mechanism is explained, and the model of full bridge topology with PCB parasitic capacitance is proposed as an example. Both the capacitance in power loops and control circuits are considered in the proposed model. Besides the capacitive loss in power loops, losses are also introduced by the capacitive coupling between the power and control circuits due to the potential pulsation of the control ground. This potential pulsation is analyzed and the calculation method of corresponding losses is presented. The formation of PCB parasitic capacitance is analyzed in detail and corresponding layout optimization methods are proposed. Theoretical analyses are verified on a gallium nitride based full bridge prototype with calorimetric loss measurement. The comparison of calculated and measured losses is presented, which shows a switching loss deviation of 26% without the consideration of parasitic capacitance and a 40% reduction on the extra losses after the proposed optimization.