LAUSR

Continuous shrinking of the size of CMOS technology leads to extremely fast devices, but the resulting interconnect structures impose so many parasitic effects that the advantage of extremely scaled and ultrahigh-speed transistors would be completely overshadowed if appropriate remedial steps are not taken. This requires an accurate and efficient estimation of interconnect parasitics and analysis of their impact on integrated circuit performance. This paper proposes a new delay model for RLC interconnect networks in CMOS technology based on a second order approximate transfer function. The proposed modeling approach includes all possible scenarios (complex poles, real poles, and double poles) in the interconnect model. Simulation results show that the proposed delay model is almost independent of the ratio of ${V}_{\mathrm { {out}}} / V_{\mathrm { {in}}}$ , and the driver resistance has significant impact on the delay. The simulation results also show that the real pole model provides better accuracy and is much faster than the complex pole model. This observation would help to optimize the values of interconnect parasitics for faster operation.