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A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

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A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A… Click to show full abstract

A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between −1.6 and −12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66–82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.

Keywords: harmonic rejection; software defined; gain boosting; current gain; front end; receiver front

Journal Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year Published: 2017

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