This paper proposes a 40-nm CMOS $2 \times {\mathrm{ VDD}}$ buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors,… Click to show full abstract
This paper proposes a 40-nm CMOS $2 \times {\mathrm{ VDD}}$ buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors, five process corners for both nMOS and pMOS could be detected. Thus, the SR deviations will be significantly reduced by controlling the switches of the output stage accordingly. Besides, leakage reduction circuit will shut down current paths to reduce dynamic leakage after signal transitions are completed. This buffer design is implemented using the typical 40-nm CMOS process, where the active area is $0.052 \times 0.213$ mm2. The measured worst case of SR variation improvement is 20.8% and 54.9% when VDDIO is 0.9 and 1.8 V, respectively. The peak dynamic leakage is reduced to 41.0% and 37.5% at 0.9 and 1.8 V, respectively.
