LAUSR

This paper proposes a mean time-to-failure (MTTF) aware design methodology for minimizing power dissipation while satisfying target chip lifetime. The key contributions of the proposed design methodology are to explicitly introduce MTTF as a design constraint and optimize the design with activation-aware slack assignment (ASA). Conventionally, the gates included in nonintrinsic critical paths are downscaled or replaced with high- $V$ th gates for power savings, where the nonintrinsic critical paths are timing paths which originally had large timing slacks before the downscaling and replacement. On the other hand, ASA gives timing slacks to nonintrinsic critical paths and reduces the number of active paths whose delays are very close to those of intrinsic critical paths whose timing slacks cannot be increased by resynthesis and sizing. The proposed optimization includes both pre-ASA circuit design and ASA implementation. The former pre-ASA design prepares several design candidates that laid out with different timing constraints and selects the most promising candidate regarding power. For this selection, every candidate is analyzed to estimate minimum supply voltage after ASA that can achieve the target MTTF. Then, the proposed methodology selects a set of flip-flops for ASA using integer linear programming, such that it reduces the sum of gatewise failure probability maximumly, and performs ASA. We evaluate MTTF of circuits with and without ASA and examine how much power saving can be obtained while satisfying the target MTTF, e.g., 10 years. Evaluation results show that the circuits with ASA achieve up to 49.6% power saving.