LAUSR

Recent developments in IC technology rely on device scaling and 3-D integration, resulting in billions of devices compacted into a small area. These trends degrade the lifetime and reliability of the system due to an increase in temperature caused by high power densities. Dynamically managing a system based on the thermal characteristics is important to mitigate this issue. An on-chip thermal-aware system composed of hundreds of distributed thermal sensors is proposed. A hybrid spintronic/CMOS-based thermal sensor is described that exploits the thermal response and small area of an antiparallel magnetic tunnel junction. The sensor cell consumes as little as 500 pJ to read 1024 thermal sensor nodes and generates a thermal map of a system composed of $32 \times 32$ thermal sensors. The sensor cell exhibits a thermal linearity ( $R^{2}$ ) up to 0.983 and a thermal sensitivity of 1.91 mV/K over the commercial temperature range of 0 °C to 85 °C while consuming $32~\mu \text{W}$ .