LAUSR

It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing D-type flip-flops (DFFs) into some gate columns. Based on the assignment of the combined gates involving the splitters (SPLs) inside each gate column in the placement stage, the passive transmission line (PTL) region between two adjacent gate columns can be formed for a set of 2-pin connections in the routing stage. In this article, given a set of 2-pin connections with their length-matching constraints inside one PTL region, based on the concept of introducing a minimal set of vias in two available layers for single-flux-quantum (SFQ) pulse integrity, an efficient via-minimization-oriented routing algorithm can be proposed to minimize the routed width of one PTL region under length-matching constraint. By separating the wiring segments into sub-segments on some connections, the corresponding segments can be first assigned onto two available layers using a minimal set of vias. Furthermore, the introduced vias on the separated segments can be assigned onto feasible positions under the non-detouring and capacity constraints, and the monotonic river-routing process can be used to minimize the region width. Besides that, a set of flexible available areas can be constructed for the extension lengths on the given connections. Finally, one extra area can be accurately estimated and inserted for the extension lengths on the given connections and the zigzag detouring paths can be inserted into the available areas to satisfy the requirement of the extension lengths on the given connections. Compared with Kito’s algorithm and Yan’s algorithm in region routing under length-matching constraints, the experimental results show that our proposed routing algorithm can use reasonable CPU time to decrease 79.9% and 43.6% of the via number and 34.5% and 12.3% of the region width for 12 tested examples on average, respectively.