LAUSR

Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is presented. The proposed implementation consists of a new “converter-free” design based on a three-level voltage stack operating at 1.8 V ± 5%. Here, the leakage current from the SRAMs in the top stack is recycled to sustain the near/subthreshold operation of the logic circuits in the two lower stacks. A test chip with the proposed voltage-stacking technique was implemented in a 28-nm low- $V{\text {th}}$ (LVT) fully depleted silicon on insulator (FDSOI) technology. The test chip is an ultralow-power advanced system-on-chip (SoC) consisting of an RISC-V core, a coarse-grained reconfigurable accelerator, and peripherals. The SoC uses a current sink and an adaptive body-bias controller for voltage regulation of the intermediate voltage rails between the stacks. The proposed system achieves up to 95% power delivery efficiency with negligible area overhead (~ 1%). The silicon measurement shows that the system energy efficiency is improved by $1.6\times $ on average, and the energy consumption is reduced by 37% on average compared to the flat implementation.