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A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time

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A fast turn-on front-end (FE) for a burst-mode nonreturn to zero (NRZ) receiver targeting vertical cavity surface-emitting laser (VCSEL)-based optical links operating at 10 Gb/s/ch is presented. Its bandwidth and… Click to show full abstract

A fast turn-on front-end (FE) for a burst-mode nonreturn to zero (NRZ) receiver targeting vertical cavity surface-emitting laser (VCSEL)-based optical links operating at 10 Gb/s/ch is presented. Its bandwidth and power are reconfigurable for energy-efficient burst-mode operation. The circuit design for 4.9 ns power-ON time using a power-gating approach is presented. Rapid power-ON is achieved using the regeneration of a high-speed latch, activated by a quarter-rate clock. Implemented in a 65-nm CMOS technology, the proposed FE consists of a shunt-feedback transimpedance amplifier (TIA), a configurable one-stage or four-stage postamplifier (PA) and an offset compensation loop. By reconfiguring the number of stages in the PA from four to one, power dissipation, and the FE bandwidth are reduced during periods of link inactivity while still maintaining sufficient gain to allow the detection of an incoming burst. The presented work is supported by simulation and measurement results with optical inputs at 10 Gb/s. The results demonstrate a 4.9-ns turn-on time, corresponding to 49 unit intervals (UIs). The overall FE dissipates 5.7 mW at 10 Gb/s (0.57 pJ/bit) and 1.9 mW during idle periods. The complete receiver of each channel occupies an area of 95 $\mu \text{m}\,\,\times81\,\,\mu \text{m}$ . A 5% area overhead is introduced by the burst sensing circuit.

Keywords: time; optical links; vcsel based; power; based optical; front end

Journal Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year Published: 2022

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