LAUSR

This brief presents a novel circuit architecture for a Dickson-based reconfigurable rectifier with wide power dynamic range (PDR). Besides, a novel figure of merit (FoM) concerning the reconfigurable rectifiers is formulated to provide a more comprehensive assessment of the rectifier’s performance. The proposed reconfigurable design improves the operating range of the rectifier by adaptively switching between the six-stage configuration during low-power operation and the 12-stage configuration during high-power operation. Fabricated in 130-nm CMOS, the proposed reconfigurable rectifier measures a PDR of 14 dB with a peak power conversion efficiency (PCE) of 34.93% for 1- $\text{M}\Omega $ load operating at 900 MHz. Relative to the recently published reconfigurable rectifiers, our design records the highest FoM of 36.98 dB/mm2, with minimum harvesting downtime.