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Path Unselection for Path Delay Fault Test Generation

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Path selection procedures identify path delay faults whose tests detect small delay defects. Path selection criteria are positive in the sense that they point to paths that should be selected,… Click to show full abstract

Path selection procedures identify path delay faults whose tests detect small delay defects. Path selection criteria are positive in the sense that they point to paths that should be selected, e.g., the longest paths. However, the longest paths are in many cases untestable, and the number of paths can be large when the longest testable paths are considered. For this scenario, it is advantageous to have a negative path selection procedure that excludes paths from consideration as targets for test generation. This provides the flexibility to identify detectable path delay faults among a reduced number of path delay faults. Such a procedure is developed in this article and referred to as a path unselection procedure. The procedure performs linear-time traversals of the circuit to unselect fan-out branches, and thus exclude from consideration paths that are shorter than the ones it keeps. It also uses available information about detectable and undetectable path delay faults to unselect fan-out branches or avoid unselecting them. To demonstrate its use, the procedure is applied to benchmark circuits as part of an iterative test generation procedure whose goal is to target manageable numbers of the longest path delay faults.

Keywords: procedure; test generation; delay faults; path; path delay; delay

Journal Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year Published: 2023

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