LAUSR

A 77 GHz quadrature frequency multiplier-by-nine is demonstrated using the 90 nm CMOS process. The implemented multiplier-by-nine is composed of a high conversion gain quadrature frequency tripler with coupled lines as the buffer stage to reduce power consumption and increase power output. This frequency multiplier-by-nine achieves good suppression for the fundamental, second, and other harmonics. The conversion loss is −33 dB at 77 GHz. The DC power consumption is only 5.2 mW. The chip area is 0.46 mm2. This device can help to improve the performance of high-frequency radar sensors.